Electronic systems are typically built from subassemblies. Each subassembly may comprise several circuit boards that are populated with active components and passive components. Passive components are electronic devices that typically require no operating power. They may, however, dissipate power. Resistors, capacitors, inductor and diodes may all be considered passive devices. Active devices typical use power to drive other parts of an electronic circuit. Transistor based amplifiers and integrated circuits are typically considered to be active elements on a circuit board.
One of the most difficult aspects of testing a fully assembled circuit board is that of identifying if an active component is operating properly. When an active device is mounted on a circuit board, it is difficult to determine if the circuit board is causing a problem or if it is the active device itself that is faulty. For instance, if an active device is attempting to drive a circuit board trace but the logic level on the circuit trace is not correct, it may be due to a short of the circuit trace to another trace or it may be the result of a faulty logic system buried deep in the active integrated circuit.
As integrated circuits became more complex, the need to support board level testability was addressed by an IEEE standard for boundary testing of an integrated circuit (IEEE 1149.1). Boundary level testing, according to modern industry trends, is accomplished by means of a test access port (TAP). The TAP port, which is often referred to as a TAP interface, allows external test apparatus to communicate over a serial interface with each input or output pin on an integrated circuit. Using the TAP interface, any given output pin integral to an integrated circuit may be driven to a particular state irrespective of the state of any functional logic element that would normally be reflected at that output pin. The TAP interface may also be used to retrieve the value perceived at an input pin. Using the serial interface, external test apparatus may read the state present at each input pin.
The TAP interface becomes useful when automated test equipment is used to identify board level faults. The TAP interface is generally used to drive the output pins of one integrated circuit in accordance with a test pattern. The TAP interface can then be used to retrieve the value perceived by an input pin on another integrated circuit. The test apparatus can then compare the perceived pattern from an input pin against the test pattern applied to the output pin to identify faults. In many cases, this technique may be used to identify the source of a fault.
TAP interface based testing has truly advanced the art of board level testing of electronic assemblies and systems. For all of its benefit, TAP interface based testing has been limited to low-rate application of test patterns. Real-time testing is simply not supported unless the system intrinsically operates at a low frequency. The TAP interface only provides for update and telemetry at a 1 MHz serial bit rate, some implementations operate at much higher frequencies.
The TAP interface is generally used to communicate with a circuit element known as a boundary scan cell. There are two basic types of boundary scan cells that have been used in the fabrication of integrated circuits; a transmit boundary scan cell and a receive boundary scan cell. The transmit boundary scan cell is typically used when testing requires that a particular pin of an integrated circuit mounted on a printed circuit board be driven to a particular state. The receive boundary scan cell is used to enable monitoring of the logic level perceived by an input pin of the integrated circuit.
Because the TAP interface operates at a relatively low frequency, boundary scan cells have been implemented to respond to a serial shift clock that is normally generated by a TAP controller, also integral to the integrated circuit. This technique for clocking data in to and out of a boundary scan cell worked well so long as the boundary scan cell was disposed immediately at the driver of an integrated circuit output pin or at the receiver of an input pin. Hence, the boundary scan cell could be treated as an adjunct appendage of the functional, application specific portions of an integrated circuit.
In many cases, the output pins of an integrated circuit must be driven at faster rates and input pins must also be equivalently monitored. In these cases, the boundary scan cells can no longer be disposed immediately at the output or input pin of an integrated circuit. In these applications, the boundary scan cells must be designed with additional cognizance of the application specific circuitry at the heart of the integrated circuit. In essence, the boundary scan cells may need to be integral with the primary functional circuitry of the integrated circuit.